1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device.
2. Related Art
In nonvolatile semiconductor memory devices such as NAND flash memories, a memory cell is processed in the finest manner on chips. When a fine pattern is to be formed in the memory cell, however, it is influenced by adjacent patterns. Because periodicity of the processing is disturbed particularly at the ends of the memory cells, it is difficult to perform the processing as designed.
To realize accurate processing at the end of the memory cell so as to have the same periodicity as that of the center of the memory cell, dummy cell arrays, on which no actual data recording is performed, are located to be adjacent to the ends of cell arrays.
The memory cell is influenced by operations of surrounding cells through a capacitive coupling of its floating gate because of its configuration. Thus, a threshold of a memory cell transistor may vary and accurate operations cannot be performed.
To make the influence of the adjacent cells upon a memory cell at the center of the cell array equal to the influence upon a memory cell at the end thereof, dummy cells that operate in the same manner as the memory cells used for storing data have to be located at the ends of the cell array.
A word line WL/a drain side selective gate line SGD/a source side selective gate line SGS of the dummy cell are connected to a word line WL/a drain side selective gate line SGD/a source side selective gate line SGS of the memory cell. The same voltages as in actual operating units are thus applied. The dummy cell is configured to share the same P-well with the memory cell. The same substrate voltage as in the memory cell is applied to the dummy cell.